The present inventive concept relates generally to digital circuit systems, and more specifically, to a synchronous digital system that prevents hold time violations.
Conventional digital circuit systems, as illustrated in FIG. 1, typically include one or more flip-flops that can be used to store state information. Primary data signals are produced according to a clock signal transition (Clock A of FIG. 2) of a system clock signal. The clock signal transition (Clock A) must be such that the receiving component can read, i.e., sample, the primary data signal by the next transition (Clock B) of the system clock signal. As illustrated in signal diagram resulting from a conventional digital circuit system shown in FIG. 2, a normal ‘low’ going data pulse is provided in response to a first clock transition (Clock A) and remains active during a full clock period, until the occurrence of the next clock transition (Clock B of FIG. 2) plus Hold Time. Digital components, however, may provide narrow output pulses that terminate before the completion of a full clock period in width. The premature termination of the pulsed data signal may result in a Hold Time Violation (refer to Data with Hold Time Violation shown in FIG. 2). The Hold Time Violation causes receiving components to miss these narrower pulses, which would normally be sampled during the next clock transition, thereby preventing the narrow pulses from being sampled.